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\ - / INDUSTRY GADFLY: "My Cheesy Must See List for DAC 2015"
_] [_
by John Cooley
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
You might want to print out a hardcopy of this as an unofficial guide to the
San Francisco DAC'15 exhibit floor. List is ranked in order of importance.
BIG DATA EDA TOOLS
1.) Given that "Big Data" has been trending as the hot new tech concept
for the past 12 months, this year's #1 Cheesy Must See Tools At
DAC'15 are easily (in order):
IC Manage Envision is a tapeout predictor based on Big Data. After
data mining 2 years of company-wide 28nm man-hours and 28nm EDA tool
run logs, Xilinx used Envision to predict their Zynq 20nm migration
tapeout to within +/- 1 week.
And, get this, by only data mining the current 20nm projects as they
progressed, Envision found 4 problem blocks (out of 40 total blocks)
holding up a tapeout and Envision predicted how much resources would
be needed to get that 20nm tapeout back on schedule. ESNUG 550 #1.
(booth 3315) Ask for Shiv Sikand. Freebie: Ghirardelli minis
Gear Design Systems is using "Big Data techniques for IR-drop/EM!".
The elusive John "Jolly" Lee, of former Mojave Quartz fame, has been
rumored to have won a RedHawk/Voltus/Gear benchmark at Broadcom by
using predictive analytics that Voltus and RedHawk completely lack.
Word is Ansys is buying Gear to beef up its ailing Apache division.
(booth 1721) Ask for John Lee. Freebie: Ansys stuffed dogs?
Cadence Indago is Lip-bu's answer to Aart's Verdi3 empire. Indago
debug works by adding Big Data Capture to Root Cause Analysis -- in
order to data mine your CDNS tool run logs -- to "highlight causality"
and correlations causing your bug in the first place. Indago's big
idea is to data mine in order to do fewer simulation reiterations.
(booth 3515) Ask Adam Sherer or Larry Melling. Freebie: Denali tix
DESIGN COMPILER & RIVALS
2.) NEW! -- Cadence Genus is CDNS' latest and newest attack on Aart's
29 year old Design Compiler monopoly in RTL synthesis. (And that's
"Genus", NOT "Genius", BTW.) Anyway it appears that Anirudh's R&D
guys have been working overtime to make a new home-grown, massively
parallel RTL & physical synthesis with "5X faster production-level
turnaround times", "1/2 iterations between unit and block/chip-
level synthesis", "timing/wire lengths with 5% of Innovus PnR",
and "20% less datapath area!". Texas Instruments, Imag Tech users.
(booth 3515) Ask for David Stratman. Freebie: Denali party tix
FUN FACT: Synopsys just recently had its 3 key RTL synthesis patents
invalidated in California Federal Court. ESNUG 547 #1. (Oops!)
Synopsys demoing both DC Explorer and Design Compiler Graphical.
Claims "10% smaller area plus reduced congestion and leakage."
(booth 2133) Ask for Gal Hasson. Freebie: pens
Mentor Oasys RealTime Designer does RTL estimation, RTL synthesis,
floorplanning, design partitioning, and pre-CTS opto all on top
of Olympus-SoC P&R. I'm not sure if MENT is selling RealTime as a
standalone RTL synthesis tool to take on Design Compiler. Intel,
TI, Broadcom, Juniper, Qualcomm used Oasys. Xilinx Vivado is Oasys.
(booth 1432) Ask for Sudhakar Jilla. Freebie: Lego Mixels
Atrenta SpyGlass Physical helps RTL designers create floorplans
for their chips pre-synthesis. It's similar to SNPS DC Explorer.
Early detection of area/timing/congestion issues. Does critical
signals, bus fabric, clock distribution, connectivity, etc.
Qualcomm, Canon, Hitachi, Renesas, TSMC, ST, Texas Instruments.
(booth 1732) Ask for Mark Baker. Freebie: remote control car
VERIFICATION IP
3.) FUN FACT: Although MENT VIP got lots of user interest in last year's
DAC, hardly anyone noticed any CDNS VIP last year -- which horribly
embarrassed Martin Lund, the Cadence VP of IP. DAC'14 #6. (Oops!)
Mentor Questa Verification IP (VIP) is a big ass library of UVM VIP.
- AMBA Family (CHI 5, ACE 4, ACE-Lite, AXI4, AXI3, AHB, APB);
PCIe Family (PCIE 4.0, PCIe 3.0, PCIe 2.0, PCIe 1.1, PIPE, PIE-8,
SR-IOV, MR-IOV, NVMe, AHCI); USB Family (USB 3.1, USB 3.0+OTG,
USB PD, PIPE, xHCI, SSIC, USB 2.0+OTG, UTMI+, UTMI, ULPI, oHCI,
eHCI); Ethernet Family (100G, 50G, 40G, 25G, 10G, 1G, 100M, 10M,
PTP, MDIO, EEE, MII, RMII, GMII, TBI, RTBI, SGMII, RGMII, QSGMII,
BASE-X, BASE-T, BASE-R, BASE-W, CAUI, XGMII, XAUI, XLAUI, RXAUI,
HI-MoM, XSBI, XLGMII, CGMII, HiGig2, FEC, Auto-Neg); Serial Family
(SmartCard, SPI-TI, SPI-Moto, SPI-NS, SPI 4.2, UART, I2C 5.0,
I2S-Philips, I2S-TI, JTAG); MIPI Family (MPHY 3.0, LLI 2.0,
DSI 1.1, CSI-3, CSI-2, DigRFv4 1.2, HSI 1.0.1, Unipro 1.6,
UFS 2.0); DDR Family (LPDDR4, LPDDR3, LPDDR2, DDR4, DDR3, DDR2,
DFI 3.1, Wide IO 2, DRAM Model Generator); HDMI Family
(HDMI 2.0, HDMI 1.4, HDCP 1.4);
Each protocol comes with a testplan, functional coverage, assertions,
examples and stimulus. ARM, Cypress, Microsemi, PLDA and ST users.
(booth 1432) Ask for Mark Olen. Freebie: Lego Mixels
Cadence Verification IP (VIP) is a mix of Verisity Specman "e" VIP
plus the Denali VIP plus homegrown CDNS VIP from consulting gigs.
- have VIP for "AMBA 5 CHI, eMMC 5.0, HDMI 2.0, LPDDR4, MIPI C-PHY,
MIPI CSI-3, MIPI SoundWire, Mobile PCI Express, PCI Express Gen 4,
USB SuperSpeed Inter-Chip, Wide I/O 2" plus new "Ethernet 25G/50G,
HBM, HMC, MIPI DSI-2, WiFi MAC".
Denali-style API, all simulated VIP runs on VCS, Questa and Incisive.
"VCS or Questa customers do not need Specman e". TripleCheck.
Broadcom, HP, IBM, Intel, LSI, Hitachi, Marvell, Qualcomm, Samsung.
(booth 3515) Ask Susan Peterson. Freebie: Denali party tix
Avery Verification IP (VIP) for PCIe Gen4, DDR4 LRDIMM/RCD2/DB2 and
3DS, MIPI CSI and DSI for C-PHY/D-PHY, eMMC 5.1, NVMe 1.2, USB 3.1
(Gen2) Superspeed+ and Power Delivery and xHCI 1.1, Unipro 1.6,
Soundwire. User Seagate, Samsung, Broadcom, Xilinx, Marvell, SKHynix
(booth 2204) Ask for Chris Browy. Freebie: cellphone charger
SmartDV VIP claims 76 VIPs. God knows what, though. (booth 514)
Synopsys Discovery Verification IP (VIP) competes in this space, but
they don't seem to be showing it at this DAC.
DIGITAL P&R
4.) Launched 12 weeks ago, Cadence Innovus is Lip-bu's new digital PnR
tool to take on Aart's ICC/ICC2. At CDNlive'15, for a 16nm 1.5M inst
design, Innovus benchmarked 20 hours vs. ICC's 104 hours. For 28nm
2.8M inst, Innovus was 48 hours vs. ICC 336 hours. (ESNUG 548 #1)
Then, at 16nm 1.8M insts Innovus took 34 hours for 8 MCMM scenarios,
while ICC/ICC2 took 121 hours. (ICC2 can't run alone; ICC2 needs an
ICC workaround.) TNS was -3.2 nsec vs. -25.2 nsec. (ESNUG 550 #1)
Claims same timing engine as Tempus. (DC/ICC/ICC2/PrimeTime all have
different timing engines.) "Timing ECO loops 50% to 60% faster!"
GigaOpt now does 5-10M inst blocks; while ICC/ICC2 1-2M inst block
size limit. Multi-threading and distributed. "Gets 20% better PPA!"
Innovus has a new GigaPlace placer. Azuro CCOpt CTS integrated in.
Users are: ARM, Freescale, Juniper, Spreadtrum, Renesas, Maxlinear
(booth 3515) Ask for KT Moore. Freebie: Denali party tickets
Mentor Olympus-SoC is showing "Project Nitro", Wally's answer to the
big ICC2 push Aart did last year. Claims 2M insts per day, new CTS,
placer, new optimizer, 5X speedup, new compact database, 5M inst block
sizes. QoR N2N, clock data opt, branch point opt, dynamic/leakage
FinFET power. Abutted floorplanning with replication support and area
reduction. Has a direct Calibre interface, double patterning. Their
Oasys RealTime Designer now with "place first" methodology where RTL
is synthesized into a virtual physical partition and placed within
the floorplan. 16/14/10nm ST, Hitachi, Nvidia are MENT Sierra users.
(booth 1432) Ask for Sudhakar Jilla. Freebie: Lego Mixels
Atoptech Aprisa keeps my interest because I'm hearing Aart's lawyers
are losing -- so ATOP is doing well both technically and legally!
Now has critical-area driven optimization, concurrent placement,
multi-point CTS, 10nm. Apogee does InHierarchy Optimization (iHO),
Multiple-Instantiated-Modules (MIM). ATOP users Samsung, Broadcom,
PMC Sierra, Xilinx. Gotta love "F.U. to ICC2 10X claims" unicorn!
(booth 624) Ask for Daniel Maung. Freebie: F.U. ICC2 unicorns
Synopsys is showcasing its IC Complier II 40nm tapeout with Toshiba
and a Monday ICC2 luncheon. Expect "game-changer" to be said often.
(booth 2133) Ask for Saleem Haider. Freebie: pens
FUN FACT: For it's recent Cortex A-72 launch, ARM got 2.6 GHz with
CDNS Innovus -- but only 2.5 GHz with SNPS IC Compiler II. (Oops!)
SPICE & AMS
5.) MENT BDA AFS is 5x-10x faster vs CDNS Spectre in ESNUG 495 #4 and 2x
faster than SNPS FineSim Pro in ESNUG 535 #3. 10+ M elements. Now
TSMC 10 nm certified. BDA ACE fully replaces Virtuoso ADE-XL for
analog characterization runs. AFS Mega does SPICE of 100+ M element
mega arrays like memories. It does DC, transient, transient with
dynamic temp, alters, sweeps, Monte Carlo. TSMC uses AFS Mega for
all 10 nm SRAMs. Samsung, MediaTek, Intel, Broadcom, Qualcomm users.
(booth 1432) Ask for Giuseppe Oliva. Freebie: Lego Mixels
CDNS Spectre-XPS is Lip-bu's comeback FastSPICE tool for memories.
Benchmarked 3-4X faster throughput than SNPS HSPICE in ESNUG 547 #3.
Has clever fast-or-accurate partitioning based on need. Multi-core.
(booth 3515) Ask for Wilbur Luo. Freebie: Denali party tickets
ProPlus NanoSpice Giga big ass capacity parallel SPICE. Did 576 M
element full-chip DRAM, 50.5 M transistor SRAM and 67 M element post-
layout SRAM. Now does 1+ B elements for 16/14/10nm FinFET or 28nm
FD-SOI. 10X faster vs. parallel SPICE. Dolphin and Attopsemi users.
(booth 1908) Ask for Lianfeng Yang. Freebie: cell phone clip
Silvaco SmartSpice is back at DAC after 10 years away! (booth 532)
EDXACT Jivaro does SPICE acceleration by netlist reduction. Reduces
netlist resistors with temperature coefficients, negative resistors,
some active devices. Mediatek, TSMC, Huawei, Toshiba, Faraday users.
(booth 2915) Ask for Mathias Silvant. Freebie: pens
Solido Variation Designer does variation-aware custom IC design for
PVT corners, 3-7 sigma Monte Carlo, hierarchical and sensitivity.
Big thing is it cuts waaaaaaay down on how many SPICE runs you need.
New 4.0 release. New GUI and CLI for memory, std cell, analog/RF
and custom digital. Users TSMC, Broadcom, Nvidia, Huawei, Cypress.
(booth 3120) Ask for Amit Gupta. Freebie: none
MunEDA WiCkeD H-MCA analyzes SRAM cell/column/array, std cell,
analog circuits for local variation to 9-sigma. Yup. 9-sigma!
Hierarchical and WCA. FinFET, Bulk, Bipolar, BiCMOS and FDSOI
Samsung, SK Hynix, ST Micro, Sanyo, Toshiba, and Altera users.
(booth 633) Ask for Andreas Ripp. Freebie: tote bags
ProPlus NanoYield is variation analysis on yield vs. PPA trade-off.
It does High Sigma Monte Carlo. Licensed from IBM seven years ago.
Can handle 10,000+ variables and does up to 7-sigma. Used by SMIC.
(booth 1908) Ask for Lianfeng Yang. Freebie: cell phone clip
Infiniscale IClys does Monte Carlo to 50X, and High-Sigma analysis
1000,000X and variability analysis of well proximity effects.
(booth 510) Ask for Firas Mohamed. Freebie: pens
Cadence Virtuoso Liberate LV/MX/Variety is rename of Altos cell lib
characterizer. Does electrical cell views for timing (NLDM), power
(NLPM) and signal integrity. CCS, ECSM, CCSN, ECSMN, AOCV/SOCV/LVF.
Likes Spectre APS. Rivals Liberty NCX, SiliconSmart, Mentor Kronos.
(booth 3515) Ask for Ahmed Elzeftawi. Freebie: Denali party tix
Integrand EMX is a 3D EM simulator for modeling on-chip passives
and interconnect and RF. Now black boxing models active circuitry.
Samsung, Broadcom, Nvida, MediaTek, TSMC, GloFlo, UMC, IBM, Fujitsu.
(booth 2117) Ask for Sharad Kapur. Freebie: stress doll
Helic VeloceRaptor/X does rapid, high capacity, electro-magnetic
inductance aware modeling of on-chip interconnect and passives.
Rapid - 3 LC tank VCO in 55 sec. High-Capacity - 2mmx300u 3 metal
clock network shielded with power mesh modeled (w/ full coupling) in
118 min on 16GB RAM machine - no layout simplifications required.
Rivals are HFSS, Momentum. Users are Qualcomm, Huawei, Freescale.
(booth 2927) Ask for Anand Raman. Freebie: squeeze baseball
IROC Tech TFIT predicts soft error FIT rate on CMOS digital cells
from SPICE netlist, GDS2, foundry models. TSMC, GF, Samsung, ARM.
(booth 2123) Ask for Olivier Lauzeral. Freebie: USB flash drive
EMULATION / ACCELERATION / PROTOTYPING
6.) Cadence Palladium XP II has full functional coverage, dynamic power
analysis, UPF/CPF, full ICE in Mhz. Sim acceleration (RTL & gates).
Virtual & hybrid, system environment virtualization, 60x faster SW
bring-up. 2.3 B ASIC gates. 512 simultaneous users. 2X faster.
TI, Broadcom, AMD, Nvidia, CSR, Freescale, Samsung, Mediatek, Sharp.
Their CDNS ARM System Development Suite is optimized for ARM v7 and
v8 based chips, HW/SW co-design, debug, interconnects, OS bring-up.
(booth 3515) Ask Frank Schirrmeister. Freebie: Denali party tix
MENT Veloce 2 does 50 MHz embedded SW execution with Warpcore, and
50 MHz SW debug with Codelink. VirtuaLAB peripherals: 256-port
Ethernet, PCIe Gen3, USB-3, SATA, SAS, VJTAG. RTL-waveform debugger.
Broadcom, Mitsubishi, NXP, ST, Trident, ZTE, HiSilicon use Veloce 2.
NEW! -- MENT Veloce 2 Power App is a super tight integration with
Ansys Apache PowerArtist. RTL power reduction analysis 4.5X faster.
(booth 1432) Ask for Jean-Marie Brunet. Freebie: Lego Mixels
Synopsys EVE ZeBu-3 claims 4X faster and can do 3 B gates. TLMs,
power-aware, simulation acceleration, ICE, synthesizable testbench.
Claims small footprint, low weight, and very modest power/cooling.
(booth 2133) Ask for Tom Borgstrom. Freebie: pen
FUN FACT: In Oregon Federal Court, Aart's lawyers lost $36 million
damages in the MENT vs. EVE Zebu lawsuit. ESNUG 538 #11. (Oops!)
ProDesign proFPGA is like SNPS HAPS but based in Germany. Mix match
Xilinx Virtex 7 330T to 2000T to Altera Arria 10. 500 M ASIC gates.
1.2 Gbps. In 2 years ProDesign shipped 336 units to 41 customers.
(booth 2923) Ask for Gunnar Scholl. Freebie: hugs
NEW! -- S2C Prodigy Cloud Cube is a chassis of 32 FPGAs for 16 users to
access 1 billion protyped ASIC gates. Ethernet access. Hot swaps.
6 global clock sources to all Logic Modules with under 200 psec skew.
(booth 3108) Ask for Richard Chang. Freebie: pens
Aldec HES-7 claims 288 M gates. Auto partitioning, ASIC-to-FPGA
clock conversion, static/dynamic probes, memory viewer, triggering,
HW breakpoints. Interfaces: Ethernet, USB, USB-OTG, HDMI, I2C, SPI,
RS232, GPIO, ARM Debug & JTAG. Qualcomm, Samsung, Fuji-Xerox, Sandia.
Their HES-DVM does System Verilog DPI-C TLM's, virtual SW, ICE.
(booth 1725) Ask for Chris Szczur. Freebie: LED yo-yos
Dini Group TOE/TOE128 is a TCP IP offload engine for high frequency
stock trading. You know, as in shares of GOOG at $539.56 is +1.2%?
Millennium IT uses it for the London Stock Exchange and Barclay.
NEW! -- Dini Group DN_ReadBacker lets you read back complete status
of your FPGA registers for debug. "No one else does this, John!!!"
(booth 2401) Ask for Mike Dini. Freebie: grumpy Mike sayings
RPP was renamed Cadence Protium, a homebrew FPGA-based prototyper.
Lip-bu's answer to SNPS HAPS. Auto ASIC-to-FPGA memory conversion,
clock tree transformation, pre-P&R model validation. "quick bring
up in 4-6 weeks instead of 3-4 months." Freescale, Nvidia, Hitachi.
(booth 3515) Ask for Juergen Jaeger. Freebie: Denali party tix
Synopsys HAPS-70 and ProtoCompiler claims 12 to 288 M ASIC gates,
2X faster, automated partitioning. 24 Xilinx Virtex-7 2000T's.
(booth 2133) Ask for Mick Posner. Freebie: pens
PLDA QuickPlay somehow plays here, but it's confusing. (booth 516)
IR-DROP / NOISE / THERMAL / POWER
7.) NEW! -- Gear DS is bringing Big Data ideas to IR-drop/noise/full-chip
power integrity analysis. Word is Ansys acquiring Gear so the former
Mojave Quartz whiz, John "Jolly" Lee, can revamp the Apache team.
(booth 1721) Ask for John Lee. Freebie: Ansys stuffed dogs?
Ansys Apache RedHawk does full-chip power integrity analysis and
sign-off, transients, simultaneous switching noise package/PCB with
distributed processing. Scalable to 16-32 machines (128-256 cores).
"500M insts with 6B resistors while keeping flat simulation accuracy"
Vector-based and vectorless. Clock jitter. TSMC 16/10 nm FinFET.
Their Pathfinder ESD does full-chip multi-domain, multipath electro-
static discharge analysis. Capacity 2M transistors with critical
path tracing to identify and fix stressed device junctions. Their
Totem does ransistor power-noise-reliability analysis. 16/14/10nm.
Apache users Samsung, NXP, ST, LSI, Applied Micro, Nvidia, TowerJazz.
(booth 1232) Ask for Ravi Ravikumar. Freebie: stuffed dog
Cadence Voltus is Lip-bu's attack on Apache/Ansys RedHawk. Full-chip
signoff, IR-drop, Power-Grid-Views. Massively parallel. 1B insts.
Works with Tempus and Sigrity chip/package/board and Innovus PnR.
Early Voltus user cut runtime 9 days to 1 day on a large ARM design.
NEW! -- Voltus-Fi now does transistor-level noise/power signoff with
Quantus QRC and MMSIM inside Virtuoso. Both Voltus and Voltus-Fi are
TSMC N10 certified. Competes vs. Apache Totem and Synopsys HSim-PWRA.
(booth 3515) Ask for Jerry Zhao. Freebie: Denali party tickets
Silvaco InVar Power/EM/IR/Thermal is their Invarian acquisition. It
rivals Ansys Redhawk/Totem. API SmartSpice integration 4-5X speedup.
(booth 532) Ask for Alex Samoylov. Freebie: tea diffuser
Magwel ESDi also does ESD analysis just like Apache Pathfinder ESD.
Checks all possible shunt paths during event; fewer false positives.
It can now handle chips as big as 10x10 mm^2 on up to 1000 pins.
(booth 2002) Ask for Olivier Dupuis. Freebie: none
Silicon Frontline ESRA also does ESD analysis like Apache Pathfinder.
(booth 323) Ask for Yuri Feinberg. Freebie: none
Entasys PadOptima optimizes the number and location of power pads to
meet your target IR-drop and SSO noise margin. Samsung, LG users.
(booth 1620) Ask for JJ Park. Freebie: pens
RTL & GATE POWER
8.) Calypto PowerPro does RTL power optimization. Users see 9% to 12%
general Verilog RTL power savings. 37% cut in sequential logic power
saving in ESNUG 535 #2. Only tool tight with Calypto SLEC-Pro
sequential equivalency checker that verifies their low power RTL
tweaks are functionally equivalent to original RTL. UPF and SPEF.
New physically-aware: models clock tree, multi-Vth libraries, SPEF
extraction of WLM. Has seen 85% correlation against gate-level.
16/14nm FinFET. Samsung, ARM, HiSilicon, Google, Freescale users.
(booth 2732) Ask for Anand Iyer. Freebie: USB charger
Atrenta Spyglass Power users got 9% to 16% power cut on Verilog RTL.
Physical awareness and better accuracy. Does ECO's, CPF, UPF,
mem in sleep mode. ERC checks on P/G netlist. UPF 2.1. Power
modeling and coarse clock gating. Marvell talk on it at DAC.
Broadcom, Cisco, Juniper, Infinera, Infineon, Qualcomm, Samsung.
(booth 1732) Ask Guillaume Boillet. Freebie: remote control car
Apache PowerArtist users saw 3% to 10% reductions. Does automatic
and guided. Sequential and combinational clock-gating constructs,
memory light/deep sleep modes, and wasted power in datapath logic.
100 M instances and clock power modeling at RTL. 16/14nm. New deep
hooks in MENT Veloce Power App. Nvidia, Samsung, ST, LSI, Ciena.
(booth 1232) Ask for Preeti Gupta. Freebie: stuffed dog
Docea Aceplorer does virtual prototyping of thermal and power at the
chip and board levels. Enables on-chip power management software
like Android Governors to work. Sony, Samsung, Intel, Nvidia, ARM.
(booth 3507) Ask for Philippe Garrault. Freebie: French candy
Cadence Sigrity does chip/package/board signal and power integrity.
Just like what Ansys/Apache Sentinel does. Lattice uses Sigrity.
(booth 3515) Ask Brad Griffin. Freebie: Denali party tickets
CDNS JasperGold Low Power App formally verifies lower power designs
that have multiple voltage and power-management domains. Checks to
see any issues the after the insertion of power management circuitry.
(booth 3515) Ask Pete Hardee. Freebie: Denali party tickets
Avery RetentSYN analyzes power transition and functional
simulation sequences in RTL and gate-level designs to auto minimize
the use of retention registers to reduce area and leakage power.
Makes optimized UPF retention register commands. Broadcom uses it.
(booth 2204) Ask for Chris Browy. Feebie: cellphone charger
LibTech ChipTimer does post-synthesis, pre-layout timing, area, power
optimization, and post-layout leakage power opto. Layout aware. 20%
to 2X less. "But we cut leakage power by 4X on a customer's 1.2M gate
16nm design using same library and no change in critical path timing."
(booth 1326) Ask for Mehmet Cirit. Freebie: none
Cadence Conformal Low Power does EC "from RTL to transistor level."
It now natively supports IEEE 1801. Qualcomm, Broadcom, Marvell, ARM.
(booth 3515) Ask Kenneth Chang. Freebie: Denali party tickets
PRIMETIME & RIVALS
9.) Cadence Tempus is Lip-bu's answer to Aart's PrimeTime STA monopoly.
50 M inst design in PrimeTime took 8.5 hours on 8 CPUs; Tempus did it
in 58 min on 32 CPUs. Generates legalized placement directives in MCMM
timing optimization for 20/16/14/10 nm placement rules. "No need for a
placement tool to legalize ECO's, it's a big boy." 100 M insts/hour.
20/16/14nm certified. Now does STA inside Virtuoso with Quantus QRC!
Users TI, Qualcomm, Broadcom, Freescale, Maxlinear, ST, NXP, Sharp, LG.
(booth 3515) Ask for Ruben Molina. Freebie: Denali party tix
Synopsys PrimeTime is world's 87% marketshare STA tool. Also does
noise analysis. This is Star-RC and SiliconSmart hooks year. ST,
Broadcom, GlobalFoundries talking at PrimeTime SIG on DAC Monday.
(booth 2133) Ask for Robert Hoogenstryd. Freebie: pens
CLKDA Variance FX generates full arc/load/slew timing derate tables
based on PVT and constraints -- 2 hours for 1000 cells per PVT corner.
Non-Gaussian variance support and early & late sigma generation.
Derates for PrimeTime, Tempus, ICC, First Encounter, ATOP, Olympus.
AOCV/POCV/SOCV/LVF 20/16/14 nm. Mediatek, Samsung, Qualcomm users.
NEW! -- CLKDA Macro FX gens derates for logic blocks like flop trays,
pulse latches, retention flops. AOCV, POCV, SOCV, Liberty tables in
minutes for complex cells. Intel, CSR, Mediatek, Samsung, Qualcomm.
(booth 3132) Ask for Isadore Katz. Freebie: tablet stylus pen
Arcadia TimeHawk STA does "1+ million inst per minute, max capacity
is 2 B inst on current release". ECO advisory, physical-aware, MCMM.
Claims super easy set-up so customers can see results themselves.
(booth 1703) Ask for Joey Lin. Freebie: tote bag
BUGHUNTERS
10.) Now that Kathryn Kranen is gone, my first bughunter question at this
DAC is: "what did Lip-bu keep after paying $145 million for Jasper?"
Cadence JasperGold is showing Coverage App that does formal linting
of your RTL. X-Propagation App formally finds "X optimism" and
"X pessimism". Low Power App measures UPF/CPF power intent, clock-
gating, retention optimization and partial retention checks. Secure
Datapath App formally finds data leaks in your chip. To check that
your ECO's are OK, use JasperGold Sequential Equivance Checking App.
(booth 3515) Ask for Pete Hardee. Freebie: Denali party tickets
Atrenta BugScope generates white-box assertions to catch coverage
holes, IP integration errors, and deep-cycle bugs and CDC errors.
BugScope nearest rival is Jasper Behavioral Property Synthesis App.
Managers love BugScope cause it test grades daily regression suites
for module-specific sanity checks of your RTL changes. Updated
Progressive App now does real-time dynamic code coverage tracking.
Users ST Micro, Marvell, Renesas, Freescale, TI, NTT, Canon, LG.
(booth 1732) Ask for Yunshan Zhu. Freebie: remote control car
Mentor Questa Formal does CDC, X-checking, auto RTL checks, formal
coverage closure, automatic property generation, connectivity checks,
CSR verification, protocols, plus sequential equivalency checking.
New formal apps: Secure Check App, Power Aware CDC, Reset Check App.
Users Samsung, Mediatek, AMD, Microsoft, Oracle Labs, HP, Micron.
(booth 1432) Ask for Mark Eslinger. Freebie: Lego Mixels
OneSpin 360-DV does full blown property checking as coverage which
"checks the checks" to direct assertions at uncovered areas. Beats
regular sim stimulus coverage. Now does SystemC -- unusual for
formal tools! Infineon, Xilinx, Western Digital, Bosch, Maxsim.
Their 360 DV Inspect combines linting with property checking, user
doesn't have to write any assertions! Their 360 EC-FPGA does
equivalency checking RTL vs. post-synthesis netlists for FPGA's.
(booth 3126) Ask for Raik Brinkmann. Freebie: Frisbee thingy
Avery PropSYN does assertion synthesis for baseline verif. metrics.
Extracts microarchitectures. "Over 15 microarchitecture functions
and 60 assertions and cover properties". Pragmas. Hitachi uses it.
(booth 2204) Ask for Chris Browy. Freebie: cellphone charger
Atrenta SpyGlass Constraints does formal false path, MCP, and clock
intent verification, SDC validation, SDC equivalence check so your
constraints are in sync with evolving design/SDCs and incremental
SDC generation. A big selling tool. Renesas, Fujitsu, TI, ST, ARM.
(booth 1732) Ask for Mark Baker. Freebie: remote control car
Real Intent Meridian CDC does billion-gate hierarchical verification;
New iDebug hierarchical intent analysis and data manager with scope-
based reporting. New glitch checks for RTL and netlists. Nvidia,
Western Digital, Lantiq users. Their Ascent Lint has 29 new rules,
DO-254 policy file for airborne hardware; deep FSM analysis. Their
Meridian Physical CDC also has a new glitch and illegal-logic checks
for gate-level netlists plus CDC checks; new faster static engines.
(booth 1825) Ask Roger Huges. Freebie: a rose
Blue Pearl Advanced CDC lets engineers visually verify and by way of
graphical FSMs, CDC and false path viewers with cross probing to RTL,
with forward and reverse tracing, and linting message filtering."
Marvell, Microsoft, Harris, Teradyne, Ciena, Xilinx, Samsung, NEC.
(booth 832) Ask for Ellis Smith. Freebie: squeeze balls
Ausdia Timevision-CDC does block/fullchip CDC analysis on RTL or
gates using SDC constraints only -- so it can verify your actual
clock groups as being CDC-safe. Chips of 20 M to 500 M inst with
1000 clocks in 8 hours. GUI user interface with full tracing.
(booth 826) Ask for Sam Appleton. Freebie: timing monkey doll
Atrenta SpyGlass CDC this year now does Reset Domain Crossing (RDC)
analysis, multimode CDC and "smarter" netlist CDC verification plus
data loss, glitch hazards, data stability, re-convergence, FIFOs.
Qualcomm, TI, ST, Panasonic, Infineon, Ericsson, Cisco uses it.
(booth 1732) Ask for Ravindra Aneja. Freebie: remote control car
Aldec ALINT does CDC rule checking. Viewer shows violating code.
(booth 1725) Ask for Ajay Pradhan. Freebie: LED yoyos
Ausdia Timevision also formally verifies design constraints. Does
gate-level and RTL SDC. 20-80M inst, with 1000+ clocks in 8 hours.
Incremental & SDC promotion/demotion. New hierarchical budgets.
New asynchronous clock/data glitch detectors. Maxim, AMCC, Nvidia.
(booth 826) Ask for Sam Appleton. Freebie: timing monkey doll
NEW! -- Excellicon ConCert-ET verifies timing intent & structural
exceptions using SVA+ and formal. ConCert does equiv checking, SDC
verification, SI and CTS analysis. 500+ M inst. Their ConMan
formally compiles hierarchical constraints for multi/merged mode SDC
for synthesis, P&R, STA tools. It extracts all root and generated
clocks, clock groups, exceptions (FP, MCP), IO's with related clock
budgeting, and case analysis values. Promotion/Demotion. Toshiba,
Renesas, Qualcomm, Sandisk, Megachip, Maxim, Microsoft, Maxlinear.
(booth 3303) Ask for Himanshu Bhatnagar. Freebie: selfie sticks
FishTail Focus merges multi-mode PrimeTime STA constraints into one
single super mode. Generate .lib models from RTL. Compare vs. what
PrimeTime extracts with netlist input. Finds clocks on the design,
the modes, and the timing exceptions for each mode. "STARC benchmark
4 M inst netlist w/ 18 modes. Made 1 super-mode. Timing correlation
100 psec pessimism & 10 psec optimism. Cut PrimeTime runtime 90%."
Now does DC, ICC, EDI, Innovus, ATOP. Users are Cypress, Altera.
(booth 909) Ask for Ajay Daga. Freebie: none
Real Intent Ascent XV does X-propagation checks. Ranks X-sources
and X-sensitive nets by failure importance. Initialization audits.
Works around VCS/NCSim/ModelSim's X-safe simulation switches. Finds
the minimally correct reset schemes; smarter reporting. Incrementals.
(booth 1825) Ask Lisa Piper. Freebie: a rose
Avery SimXACT automatically find X bugs in RTL and eliminates false
X's in gate-level simulation. New gated clock X pessimism analysis
and auto generated fix deposits. Verdi App to graphically view
force/release fixes as well as any real X backtrace logic cones.
(booth 2204) Ask for Chris Browy. Freebie: cellphone charger
Mentor Visualizer Debug is Wally's debug answer to Cadence SimVision
Debug Analyzer and Synopsys DVE/Verdi. Visualizer debugs RTL, gates
and testbenches, automatic tracing to "pinpoint cause of errors".
(booth 1432) Ask for Gordon Allan. Freebie: Lego Mixels
Synopsys Verdi3 is the wildly popular design debug waveform viewer
with a Qt-based GUI. Aart got it with SpringSoft. Man, it does
everything! UVM, OVM, System Verilog, VHDL, SVTB, VMM, SVA, CDC,
FSBD, UPF/CPF, nWave, nSchema and TFV, PDML, CTS, SDC, STA, HW/SW.
(booth 2133) Ask for Thomas Li. Freebie: pens
VIRTUOSO & RIVALS
11.) Virtuoso Layout EAD does real-time in-design fast RC extraction.
Random walk capacitance solver, EM checking, finite-element mesher
for resistance, current limit/budget checks. Also does parasitic
re-simulation of partially completed layouts. Layout engineer gets
immediate feedback on layouts to avoid "rip and repair" syndrome.
New current distribution display, IR drop analysis across the design.
Their Virtuoso Shape-Based Router hypes up chip assembly this year
plus the Virtuoso Wire Editor and "pin-to-trunk router in full-color
aware mode" plus "EM-aware trunk optimization and EM-driven routing".
New "Routability Checker for chip assembly and block to block flows."
Samsung, Renesas, Analog Devices, Allegro Systems, IBM, ST, eMemory
(booth 3515) Ask for John Stabenow. Freebie: Denali party tix
Virtuoso Advanced Node now for 16nm, 16FF+ and early 10nm adopters.
Does SADP coloring and MPT. 200 CDNS R&D engineers been working on
this for 3 years. Also talking at TSMC and Samsung booths on 10nm.
(booth 3515) Ask for Jeremiah Cessna. Freebie: Denali party tix
Virtuoso IPVS does on-the-fly signoff DRC checks as you design. It
does DPT odd loop detection with fixing hints for designers at
16/14/10nm FinFET/FDSOI flows. Annotation Browser cross probing.
Renesas, Cortina, ST uses IPVS. (booth 3515) Ask Manoj Chacko.
WOW! -- Silvaco Expert is a hierarchical IC layout editor. Schmatic
driven. 10 Gig GDSII loads in "minutes". Uses Calibre Interactive
for DRC "on the fly". Rapid pan/zoom. Equal Resistance Router.
(booth 532) Ask for Marc Polito. Freebie: tea diffuser
Pulsic Animate does automatic layout of analog (transistor level)
designs, with no constraints, no scripting, no programming required.
Multi-threaded. Makes 100's of fully PnR-ed layouts in minutes from
an OpenAccess schematic (vs. 2-3 weeks single layout in Virtuoso).
Did a 40% reduction in cell block implementation time for Ricoh.
(booth 1126) Ask for Keith Sabine. Freebie: stuffed panda
Synopsys Custom Designer and Laker3 are Aart's two different answers
to the CDNS Virtuoso monopoly. Fujitsu and TSMC are Laker3 users.
(booth 2133) Ask for Dave Reed. Freebie: pens
Tanner EDA had OA-based S-Edit schematic capture, L-Edit custom
layout, HiPer Verify DRC, and T-Spice SPICE plus an AMS-focused
digital HiPer AMS. Founded 1988. Known for "cost effective" prices.
Was recently bought out by MENT. What tools will remain, if any?
(booth 1626) Ask for Jeff Miller. Freebie: MENT Lego Mixels?
Analog Rails, the "R.I.P. Virtuoso" start-up, is a full custom
OA-based schematic, layout, SPICE, optimization, compactors, nudgers,
placers, routers, DRC/LVS, RCx, EM, IR drop, and differential-aware
tilers. AUTOMATED analog design plus everything is synchronized;
schematic, layout, SPICE, DRC, all constantly share the same info.
(booth 1417) Ask for Cliff Wiener. Freebie: stolen CDNS pens
NanGate Library Creator fine tunes std cells for slow transitions,
power, voltage. Also multi-bit cells (saves 25-30% dynamic power,
20-25% leakage), CPU/DSP datapath (8-14% less area). 20/16/14 nm.
(booth 2221) Ask for Jens Michelsen. Freebie: pens
ClioSoft Visual Design Diff compares two versions of a schematic or
layout by graphically highlighting differences directly in Virtuoso
Supports IC 5.x (CDBA) and IC 6.x (OpenAccess). Does hierarchical.
Work with DesignSync & IC Manage. Can suppress cosmetic changes.
Batch mode to run diffs in the background and save state for later.
Infineon, Qualcomm, Bosch, Northrup, Marvell, Toshiba, TSMC, Vitesse.
(booth 3327) Ask for Karim Khalfan. Freebie: water bottles
MunEDA WiCkeD RELAGE optimizes analog/RF/IO circuits for reliability.
keep control over Vth/mobility degradation while optimizing speed and
power. Qualified for FinFET, Bulk, Bipolar, BiCMOS, and FDSOI.
Ver 6.7 STMicroelectronics, Infineon, Altera, Microsemi uses it.
(booth 633) Ask for Michael Pronath. Freebie: tote bags
ClioSoft SOS RF does design data management DDM for RF engineers
using Keysight Agilent ADS. No one else does that! Triquint uses it.
(booth 3327) Ask for Amit Varde. Freebie: water bottles
RTL SIMULATORS
12.) Rocketick RocketSim parallelizes your Verilog simulation into multi-
threads on 100's of regular multicore XEON Servers. Runs 23X faster
than CDNS Incisive, SNPS VCS, MENT Questa. Does both gate and RTL
sims. Compiles 1B gates in 2 hours. 4-state-logic for X. Now does
full System Verilog and accelerates SVAs. Intel, Nvidia investors.
(booth 3102) Ask Uri Tal. Freebie: backpacks
NEW! -- Verifyter PinDown auto debugs regression failures by IDing the
commits that cause the test failures and automatically assigns bug
reports to the engineers who made these commits. Broadcom uses it.
(booth 2604) Ask for Christian Graber. Freebie: candy
MENT Questa Platform bundles all Mentor Verilog/VHDL RTL simulation,
emulation, low power, VIP, traffic generators, interconnect test,
intelligent testbench, coverage, UVM, formal in one big smudgy bundle.
(booth 1432) Ask for Tom Fitzpatrick. Freebie: Lego Mixels
CDNS System Development Suite bundles all the Cadence RTL simulation
stuff "virtual prototyping, RTL sim, acceleration & emulation, FPGA
prototyping, accelerated verification IP, JasperGold, Specman e, HLS."
plus "Hybrid of VSP and PXP boots Linux 60x faster than PXP by itself.
Users bring up Android and run AnTuTu benchmarks pre-silicon."
(booth 3515) Ask for Juergen Jaeger. Freebie: Denali party tix
SNPS Verification Continuum bundles all the Synopsys simulation stuff
yada, yada, yada... exactly like the MENT and CDNS marketing above...
(booth 2133) Ask for Manoj Gandhi. Freebie: pens
Aldec Riviera-PRO simulates System Verilog, VHDL, Verilog and SystemC.
Plot Viewer does simple/polar/vector graph and image/color map. Now
has new Python support using Cocotb GPI. Enables terse, readable,
maintainable code while providing easy Python abstraction to RTL.
(booth 1725) Ask for Satyam Jani. Freebie: LED yoyos
Defacto Star Design tools is an 8-part unified RTL design flow where
coherency between Verilog/VHDL RTL, SDC, IP-XACT, UPF, and SystemC
is guaranteed. Builder does RTL design editing and exploration.
Checker does simulation-free connectivity checks. Low Power does
UPF design exploration. Other parts do padring, DFT, IP, etc. See
review in ESNUG 530 #2. Users Qualcomm, Broadcom, Intel, Maxim-IC.
(booth 1902) Ask for Chouki Aktouf. Freebie: Swiss knives
Amiq DVT Debugger Add-On is an add-on to VCS/Questa/Incisive to let
an engineer NOT have to continuously switch between his editor and the
"e"/SystemVerilog/VHDL simulator. IDE is sorta Visual C like stuff.
Cavium, Cisco users. Specador auto generates HTML documentation.
(booth 1419) Ask for Cristian Amitroaie. Freebie: none
Agnisys DVinsight is a friendly editor for UVM developement sort of
like Amiq. Helps your write code. And their IDesignSpec converts
specifications for Registers/Sequences into UVM/RTL. NASA, Intrinsix,
HGST, Icron, Conexant, Wipro, Conexant, John Deere, CERN uses Agnisys.
(booth 2509) Ask for Anupam Bakshi. Freebie: beer bottle opener
NEW! -- Potential Ventures XACTLY tool flow for RTL SW/HW development.
Generates docs/sw/rtl/testbench, co-simulate production software,
auto-discover hardware components, interactive debug tools, etc.
(booth 1725) Ask for Chris Higgs. Freebie: "hugs"
IP TOOLS
13.) IC Manage GDP IP Pro maximizes your internal IP reuse -- it can be
a mix of homebrew and purchased IP. Trace bug dependencies. Fixes
across all IP revs and designs. Bug history viewable. Checklist
driven design, testbench reuse. Broadcom, Nordic Semi, Samsung.
(booth 3315) Ask for Anthony Galdes. Freebie: Ghirardelli minis
ClioSoft SOS IP is where designers can create and upload IPs,
browse, search and compare available IPs, easily track the IP lineage,
issues, defects and their resolutions. New web-style GUI this year.
(booth 3327) Ask for Karim Khalfan. Freebie: water bottle
Methodics ProjectIC does IP lifecycle management. From creation
through to integration. Release management, usage tracking, plus
parent/child relationships), and a dynamic IP catalog for engineers.
(booth 1114) Ask for Vishal Moondhra. Freebie: none
Atrenta GenSys does IP integration, chip assembly, automated RTL
generation. Competes against Synopsys CoreAssembler or Duolog Weaver
or Magillem Platform Assembly. Claims 20-30X faster than IP-XACT.
"Integrate 64-bit ARM Cortex cores in your chip in days, not months."
TI, Sandisk, Broadcom, ST Microelectronics, LG, Canon, Renesas.
(booth 1732) Ask for Kiran Vittal. Freebie: remote control car
Mentor Novelics MemQuest is Wally's answer to SNPS DW Memory
Compilers. It's a web-based custom memory IP generator optimized for
low dynamic power, low leakage, high density, speed memories. Auto
self-repair, auto leakage reduction, and "routing-friendly" memory
IP generation. Single or multi-PVT corners. MUXing and banking.
(booth 1432) Ask for Farzad Zarrinfar. Freebie: Lego Mixels
CALIBRE, STAR-RC, & RIVALS
14.) Calibre nmDRC does 10 B devices full reticle 10nm designs in 9.6 hours
overnight. Triple patterning, Self-Aligned Double Patterning (SADP),
hot spot pattern matching detection, voltage aware spacing. It's the
Golden DRC/LVS sign-off at Samsung, TSMC, GlobalFoundries, and UMC.
(booth 1432) Ask for John Ferguson. Freebie: Lego Mixels
Calibre RealTime lets engineers do instantaneous sign-off DRC during
digital PnR inside ICC (ESNUG 538 #4) and Laker (ESNUG 529 #4).
"Same deck, same results as batch Calibre." Does double patterning,
pattern matching, voltage-aware DRC, density checks. 20/16/14 nm.
(booth 1432) Ask for Srinivas Velivala. Freebie: Lego Mixels
Cadence Quantus QRC competes with Star-RCXT and Calibre-XRC. It
does multi-corner/statistical/inductance RLCK extraction, 16/14 nm
modeling, distributed processing, netlist reduction, SNA. Yeehaw!
Double patterning, 3D-IC, FinFET and FD-SOI extraction, reliability.
Constraint validation. Works "in-design" in Innovus and Virtuoso.
(booth 3515) Ask for Hitendra Divecha. Freebie: Denali party tix
NEW! -- Mentor Calibre xACT does massively parallel full chip RLC
paracitic extraction without tiling. Processes entire net on a
dedicated CPU. No boundary and halo effects. Also has a 3D field
solver. Qualified for 14/16nm by Samsung and TSMC. Cypress user.
(booth 1432) Ask for Karen Chow. Freebie: Lego Mixels
EDXACT Belledonne compares layout versus layout, quickly finds the
differences with respect to wiring, and tells if diff is important.
(booth 2915) Ask for Mathias Silvant. Freebie: pens
Sage iDRM is a physical design rule compiler. It finds all places
in your physical design where your "test" rule applies -- plus where
it's been violated. It helps make sensible DRC decks. DRVerify
does DRC runset verification. Generates test cases systematically
covering all boundary conditions of that design rule. DRM2PDK
generates Pcell physical params. 22nm - 10nm. Lattice uses Sage.
(booth 1924) Ask for Coby Zelnik. Freebie: none
Coventor SEMulator3D is a tool for the fabs themselves to simulate
the manufacturing process. Virtual fabrication. Test effects early.
(booth 3310) Ask for David Fried. Freebie: none
MARGINs & ECOs
15.) Dorado Tweaker is a family of physically-aware ECO tools:
Funct. ECO / Timing ECO / Power ECO / Metal ECO / Clock ECO
Tweaker-F1 / Tweaker-T1 / Tweaker-P1 / Tweaker-M1 / Tweaker-C1
Synopsys PrimeTime-ECO vs. Tweaker-T1
Cadence Conformal-ECO vs. Tweaker-F1
Static/dynamic power ECO's. 50 M inst. 16/14/10 nm FinFET designs.
Broadcom, Qualcomm, LSI, LG, TSMC, Mediatek, Samsung, Altera users.
(booth 1614) Ask for JJ Hsiao. Freebie: magic ball
ICScape TimingExplorer is a physically-aware MCMM timing ECO tool.
Now does PBA-based timing fixes, and route-based timing fix. And
their ClockExplorer does CTS clock analysis/constraint generation.
(booth 1602) Ask for Jason Xing. Freebie: letter opener
Cadence Conformal ECO Designer now generates "congestion-aware ECO"
for "last-minute difficult ECO areas". Broadcom, Qualcomm, Cisco, ST.
(booth 3515) Ask Kenneth Chang. Freebie: Denali party tix
Synopsys PrimeTime DMSA is all about distributed MCMM timing ECO's.
(booth 2133) Ask for Robert Hoogenstryd. Freebie: pens
SystemC/C/C++/TLM STUFF
16.) Calypto Catapult 8.0 synthesizes SystemC/C/C++ into Verilog/VHDL RTL.
New multi-year re-write. Now "top-down" and "bottom-up" synthesis
control over which regions are optimized. ASICs or FPGAs. ECOs.
Incremental. Better SLEC-Pro equiv checker hooks. Catapult-LP
more accurate for RTL power, micro-architectural tradeoffs for PPA.
Catware synthesizable parameterizable IP source code for 25 FFT and
filters. Qualcomm, Nvidia, ST, Google, Fujitsu, Hitachi, Toshiba.
(booth 2732) Ask for Mark Milligan. Freebie: cellphone charger
Cadence Stratus HLS takes in untimed SystemC/C/C++ to generate Verilog
RTL that Design Compiler or CDNS Genus can easily digest. The rumor
is it's 90% Forte Cynthesizer with 10% old C-to-Silcon; a weird hybrid
of the two tools. Samsung, LG, Sony, Realtek, Toshiba, Ricoh users.
(booth 3515) Ask for Brett Cline. Freebie: Denali party tix
Synopsys Synphony C plays here but probably not showing at this DAC.
Calypto SLEC does SystemC/C++/C-to-RTL functional equivalence. Tight
EC with Catapult; less tight vs. SNPS Synphony or CDNS Stratus. Also
C++ assertion/property checks. Now runs "bottom up" to do partitions.
(booth 2732) Ask for Thomas Bollaert. Freebie: cellphone charger
Real Intent Ascent Lint works with MathWorks HDL Coder synthesis and
Calypto Catapult synthesis; does hierarchical waiver management.
(booth 1825) Ask Lisa Piper. Freebie: a rose
Carbon Performance Analysis Kits are pre-built virtual prototypes
and software for ARM Cortex-A9/A15/A7/A57/A53/A72 emulation. Also
CCI-400, DMC-400, GIC-400, NIC-301, etc." Competes vs. emulators.
Samsung, Broadcom, ST, ZTE, Huawei, Mediatek, Altera, Mediatek users.
(booth 1815) Ask for Bill Neifert. Freebie: none
Fraunhofer COSIDE is a system level tool based on SystemC as well
as on SystemC AMS 2.0. Competes vs. Matlab Simulink or MENT Vista.
(booth 810) Ask for Karsten Einwich. Freebie: cookies
Breker Cache App gens multi-threaded, multi-processor, multi-memory
C tests for cache coherency & processor-memory workload performance.
Verdi debug. Users Broadcom, IBM, Nvidia, ST Micro, ST-Ericsson.
(booth 3209) Ask for Tom Anderson. Freebie: compass keychain
Codasip Framework is ASIP (application processor) dev environment
that generates a C/C++ compiler, debugger, synthesizable RTL and UVM
based verification. Competes vs. Tensilica & Synopsys ASIP Designer
(booth 1814) Ask for Neil Hand. Freebie: notepads
Mentor Vista CodeBench is a SystemC/TLM platform for prototyping and
optimizing messed up HW architectures. "throughputs and resources,
memories and caches, bus latencies and load capacities" and "VPK's
for Altera Arria V, Xilinx Zynq, Freescale I.MX6, ARM. Automative.
(booth 1432) Ask for Rami Rachamim. Freebie: Lego Mixels
Imperas does virtual platform based software development, debug and
test. Acceleration on multicore hosts. It competes against Cadence
Virtual, Synopsys Virtualizer, Mentor Vista, and Wind River Simics.
Imag Tech, Renesas, Recore, Altera, NIRA Dynamics, AMD, USAF users.
(booth 2414) Ask for Jim Straus. Freebie: none
Intel CoFluent Studio does HW/SW system modeling in "intuitive"
graphical notations written in ANSI C/C++ code. Intel uses it.
(booth 2008) Ask for Andy Grove. Freebie: paranoia
HARD & SOFT IP
17.) ARM Ltd has its annual 16 vendor orgy -- Ansys, Carbon, eSilicon,
Imperas, Lauterbach, Magillem, Mentor, NetSpeed, Rambus, Sonics, and
Synopsys -- all taking turns in the money shots. (booth 2414)
ARM, Inc. is showing its hot sexy new Cortex A-72 plus its other
32/64-bit RISC CPU's, memory IPs, std cell libs, plus ARM Socrates DE
(which it bought last year) for rapid IP configuration & SoC assembly,
plus ARM Coresight Creator plus ARM CoreLink Creator. (booth 2428)
Synopsys sells Virage DW ARC 600 & 700 family of cores, plus Virage
mem IP, plus Virage InChip std cell libs that all directly compete
against ARM. 190 customers. DW ARC comes in low power and audio.
(booth 2133) Ask for Mike Thompson. Freebie: pens
Cadence IP Portfolio has interface IP for USB, PCIe, MIPI, Ethernet;
analog mixed-signal IP for SerDes, ADC, DAC, AFE, power management;
peripheral IP for I2C, I2S, PWM; Denali memory IP for DDR, LPDDR,
WideI/O, NAND Flash; Tensilica for baseband, audio, imaging/video.
(booth 3515) Ask for Martin Lund. Freebie: Denali party tix
NanGate IoT Std Cell Libs are "IoT optimized" full custom libraries.
9000 cells, 5 VTs, 3 gate lengths. 28/40/65/90nm silicon proven. Cut
area by 8-14%. "Our 8T 28nm GF lib got 55% higher raw gate density."
(booth 2221) Ask for Jens Michelsen. Freebie: pens
NEW! -- Cadence TenSilica Fusion DSP is a DSP for IoT and basic control
functions. 16-bit quad MAC, FPU, AES encryption, standard options
(memory types and structure, I/Os, interfaces) plus ARM or MIPS CPUs.
Used in Epson GPS watches, Toshiba IoT uP, Megachips IoT sensor hubs.
(booth 3515) Ask for Neil Robinson. Freebie: Denali party tix
NEW! -- Sonics ICE-Grain Power Architecture is configurable IP blocks,
embedded control SW, etc., to do dynamic on-chip power management.
(booth 3501) Ask for Drew Wingard. Freebie: USB drives
NEW! -- Cadence Multi-Protocol PHY is multi-protocols on single PHY
macro. Complies PCIe (Gen 1-4), Ethernet (10G-KR, XAUI, QSGMII, XFI,
SGMII), USB 3.x, MIPI M-PHY v3.0, SATA 3.1, DisplayPort (DP) v1.2a.
"It's much better than a different PHY for every interface."
(booth 3515) Ask for Osman Javed. Freebie: Denali party tix
Analog Bits is what its name implies: low power, small footprint
28 nm IP for precision clocking, PLL, DLL, SERDES, SRAM, TCAM, IO.
(booth 2127) Ask for Mahesh Tirupattur. Freebie: none
CAST has a mess of 8051 cores, GPU and accelerator IP cores, CAN FD,
H.264 Video encoders, JPEG IP. (booth 1026) Ask Nikos Zervas.
Codasip Codix IP competes vs. TenSilica and ARC. 16-bit cacheless
DSP, 32-bit RISC, 6-stage 32-bit VLIW. (booth 1814) Karel Masarik.
Cortus SA sells ultra low power 32-bit microcontoller IP cores; four
types: RISC to floating point. (booth 2503) Ask Michael Chapman.
Ensilica Ltd. sells configurable 16/32-bit eSi-RISC, eSi-Crypto,
eSi-Comms, eSi-Connect. (booth 2228) Ask for Ian Lankshear.
PLDA sells IP for SuperSpeed USB, PCI Express, PCI-X, 10Gb TCPIP
for ASICs and FPGAs. (booth 516) Ask for Vijay Polavarapu.
Silicon Creations LLC sells Fractional-N PLL and SerDes IP that's
"proven on 20 process nodes". (booth 2402) Ask for Micke Wersall.
True Circuits sells IP for low-jitter PLLs and DLLs for TSMC, UMC,
GloFlo, CP 180nm to 16FF+. (booth 2014) As for John Maneatis.
TEST/SCAN/BIST/JTAG/FAULTS
18.) Mentor Tessent IJTAG does "efficient production test and support for
in-system Power-On Self-Test for ISO 26262 used in auto and other
industries." Most of Wally's test brainiacs rather be at ITC, but
if you find one at DAC, ask him/her to explain IJTAG. Neat stuff!
(booth 1432) Ask for Steve Pateras. Freebie: Lego Mixels
Atrenta SpyGlass DFT does "RTL analysis for stuck-at/at-speed
testablity, low power design, JTAG/IEEE1500" and "RTL fault coverage
estimation for stuck-at, transition and random-resistive faults."
Qualcomm, Samsung, Apple, TI, ST, Mediatek, Canon, Cisco users.
(booth 1732) Ask Kiran Vittal. Freebie: remote control car
WinterLogic Z01X Safety does fault injection and simulation (DC, AC,
transient faults) for ISO 26262 cert and IEC 61508 compliance.
Automotive ISO 26262. It rivals SNPS Certitude & CDNS Verifault-XL.
Users Denso, Melexis, Renesas, Toshiba, Xilinx, Yogitech, Freescale.
(booth 1914) Ask for Jason Campbell. Freebie: mini RC-car
FPGA STUFF
19.) Mentor Certus does silicon debug for FPGAs, FPGA Prototypes and ASICs.
It rivals Xilinx ChipScope, Altera SignalTap, Synopsys Identify.
"Traced 500 AXI bus signals of a Linux boot sequence (180 seconds)"
(booth 1432) Ask for Michael Sachtjen. Freebie: Lego Mixels
NEAT! -- Menta Origami Designer is a unique tool that lets designers
create their own 28nm FPGA. Rivals are NanoXplore and Flex Logix.
(booth 2716) Ask for Jean-Louis Brelet. Freebie: honey candy
NEW! -- Atrenta SpyGlass FPGA does RTL lint and CDC for FPGA designs.
(booth 1732) Ask Kiran Vittal. Freebie: remote control car
OneSpin 360 EC-FPGA does equivalency checking RTL vs. post-synthesis
netlists for FPGA's. (booth 3126) Ask for Raik Brinkmann.
ROLL-YOUR-OWN EDA SOFTWARE STUFF
20.) Verific sells System Verilog and VHDL parsers with C++ interfaces to
EDA developers. Perl interface. Parsers for UPF 2.1, PSL, EDIF.
Python APIs. Synopsys, Atrenta, Xilinx, Altera, AMD, Infineon users.
(booth 2714) Ask for Michiel Ligthart. Freebie: stuffed giraffe
NEW! -- Invionics Invio EDA Tool Platform lets users build their own
custom EDA tools. Python and Tcl API's. System Verilog and VHDL.
RTL and netlist modification, functional verif, UVM, IP-XACT.
(booth 2507) Ask for Brad Quinton. Freebie: none
NEW! -- OneSpin 360-DV LaunchPad lets companies with no formal tools
develop/deliver formal-based apps inside their own in-house EDA SW.
(booth 3126) Ask for Raik Brinkmann. Freebie: Frisbee thingy
WORKSPACE & DESIGN DATA MANAGMENT
21.) IC Manage Views lets engineers get their EDA tools populated on their
desktop very quickly. Claims "1 gigabyte, 10,000 file work-space
in 1 second to populate." Broadcom benchmark saw 2 GB in 15 sec.
Their GDP does data management for digital and custom designers to
find, modify, release and track design data through to tapeout.
Samsung, Altera, AMD, Maxim, Nvidia, Broadcom, CSR are users.
(booth 3315) Ask for Alex Tumanov. Freebie: Ghirardelli minis
ClioSoft SOS does HW configuration management and rev control for
Virtuoso, Laker, Pyxis, Custom Designer, Keysight ADS. Built-in IP
management and reuse. Does soft integrations with in-house flows.
Huawei, Google, Analog Devices, Infineon, Toshiba, Marvell, CERN
(booth 3327) Ask for Karim Khalfan. Freebie: water bottle
Methodics VersIC from Missing Link acquisition. Users request a
release from Cadence or Synopsys UI. Release candidate must be
verified and released only if it passes quality tests. Then added
IP repository. Stops bad release bringing whole design team down.
NXP, Cirrus, Cisco, Samsung, Google, Huawei, Microsoft, Boeing.
(booth 1114) Ask for Vishal Moondhra. Freebie: none
Runtime FlowTracer automates your design flow across 1000's machines.
Compute farm record 1.5 M jobs, 18 M files in 1 single customer flow.
License and network montoring products, too. Competes vs. LSF/GRID.
New this year "secure EDA in the cloud" collaboration with Zentera.
(booth 1227) Ask for Andrea Casotto. Freebie: stuffed foxes
Anyway, I hope this helps! I'm easy to spot: just look for the tall, fat
confused white guy who looks like he shouldn't be there. That's me! :)
- John Cooley
DeepChip.com Holliston, MA
P.S. And if you found this floor guide useful, please email me. It's a LOT
work at a VERY crazy time of year for me to put this together.
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John Cooley runs DeepChip.com, is a contract ASIC designer, and loves
hearing from engineers at or (508) 429-4357.
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