( DAC'18 Item 3 ) ------------------------------------------------- [01/23/19]
Subject: Real Intent smacks Synopsys CDC & RDC signoff as #3 "Best of 2018"
SEIZING SIGNOFF: I have to tip my hat to Prakash Narain, founder and CEO of
Real Intent, for stepping up his game against Synopsys Spyglass ever since
Aart bought Atrenta.
The past two "Best of" had RI doing well with:
Real Intent trounces Synopsys Atrenta as the #6 "Best of" for 2017
Real Intent and Blue Pearl get #2 overall for Best EDA of 2016
These "Best of" 2018 user comments (below) had a 54% jump in user mindshare.
User word count for all Real Intent products
2018 : :######################################### 2046
2017 : :########################## 1328
The even bigger jump (132%) was for Prakash's newer Spyglass-killer tools,
Verix Multimode CDC and Meridian RDC.
User word count for Real Intent Verix CDC and Meridian RDC
2018 : :###################### 1104
2017 : :########## 475
GOODBYE LINT: Yea, for years Real Intent's been known as that "rival linter
that goes against Atrenta Spyglass", but Prakash has pushed his company to
be more of a "must-have signoff tools you gotta have" company -- or at least
he's getting that reputation with user comments about his new multimode CDC
signoff (Verix CDC) and his newish RDC signoff (Meridian RDC) tools.
(Conversely, I know SNPS sales claims to have RDC and multimode CDC, but
I've yet to have a single EDA user writing in confirming if these two
claimed functionalities are actually useful or not.)
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QUESTION ASKED:
Q: "What were the 3 or 4 most INTERESTING specific EDA tools
you've seen this year? WHY did they interest you?"
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(SCOOP!) USER ON NEW MULTIMODE STUFF (Verix CDC)
Verix CDC
We use Real Intent's Verix CDC tool for multi-mode RTL CDC analysis of
our large blocks, with dozens of separate IPs and all their associated
top-level clock selection and reset logic.
We've run Verix on designs with up to millions of flops and dozens of
clocks.
We've already been using Real Intent's Meridian CDC tool for years for
our IP-level single-mode RTL CDC analysis. At the IP level, setting up
clocks is relatively simple; most clocks drive directly from input ports
to flops, and a single-mode analysis is practical and sufficient.
The more complex clock selection logic is at the top level, outside the
IPs themselves.
We use our large-block Verix CDC flow to focus on paths between IPs and
other top-level logic.
- We were previously not analyzing these top-level paths for CDC
issues until much later in our flow, during backend signoff
checks. (At that point, our CDC checks are more simplistic.)
- However, constraints are more complex in the backend because
the design includes all the clock selection logic, and the
constraints need to account for all the potential clocking
combinations allowed by the clock selection logic.
- Therefore, as part of trying to expose all potential clock domain
crossing issues as early as possible, we give Verix CDC
constraints that are similar to the ones we use for backend
timing signoff.
- Verix can handle these constraints with a multi-mode analysis.
This allows multiple clocks to be propagated to each flop;
the tool then automatically derives logical and physical
exclusivity to cut down on noise in the violation reports.
Besides its multi-mode capability, Verix CDC is very similar to Real
Intent's Meridian CDC tool in terms of scripting, reporting, and the GUI
debugger. One area of ongoing improvement for both tools is the speed
and utility of the native tool commands and attribute access. This is
becoming more important as we are simultaneously developing more
sophisticated custom scripts and moving to cover larger designs.
Both Meridian and Verix do much more than just enumerating all the clock
domain crossings.
Their CDC analysis can associate control and data crossings into
interfaces, check whether control crossings are fully protecting their
related data crossings, looking for potential glitch issues, downstream
reconvergence issues, etc.
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USERS ON NEWISH RESET STUFF (Meridian RDC)
Meridian RDC
It's main value for us is identifying metastability issues/bugs across
reset domains while still at the RTL level.
It can also help detect reset glitches and reset correlation issues
across clock domains.
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Real Intent Meridian RDC
Takes in RTL code and reports asynchronous reset domain issues.
It's a tool my company is interested in looking at.
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Real Intent Meridian RDC
We did a one-month evaluation of Real Intent Meridian RDC for static
analysis of reset domain crossings. We ran the static checks on an DSP
vector-processing engine, using it to clean up our design.
Based on the eval, our team preferred Meridian RDC over our existing
tool. Below is my specific feedback.
Ease of use
It was easy to use and fast -- it only took one day for us to set
it up and get it running for our designers to do their analysis.
Reports
The feedback from the tool was pretty straight forward, and it was
relatively low noise vs our other tool. The warning and violation
reports looked precise.
Performance
Meridian RDC's speed was good. Our IP Block was a complex DSP
engine -- and took only 19 minutes to run.
Cases covered
It appeared to cover reset meta-stability, reset glitch, and rest
correlation cases well.
- The tool identified ~ 3000 paths in the design that had
safe crossings due to proper clock gating.
- 1000 metastable crossing cases with issues due to
deprecated partial async domain handling in RTL. 700 were
due to a soft reset feature being added to the IP which
needed to be flushed out.
GUI & Navigation
The tool's GUI and navigation made it efficient to get to the crux
of the RDC violations.
- The schematics do a nice job of pinpointing the violation
in a graphical way. They show a structural representation
of the violation to help us understand the cause.
- In one case, it turned out that our partial asynchronous
reset event caused a glitch to permeate to the logic in
the rest of the chip not being reset which would have made
the soft reset feature unusable.
- For debug, we can look at the analysis with spreadsheet
filter -- easy to do post-processing.
We'd like to see two enhancements for ease of use. First, we'd like to
be able to easily apply the waivers we have at a lower level of
hierarchy at a higher level of hierarchy. Right now, if an IP block is
instantiated in another module, and that IP came with a waiver, you must
condition the waiver to make it work. We'd also like a mechanism to
model or constrain a hard macro.
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The dynamic check add-on in Meridian RDC.
Meridian RDC has a good engine for static reset check, which serves as
a good basis for their dynamic checks add on.
This runtime engine in Real Intent can be programmed to create new
custom rules -- i.e. the IP may look OK structurally for RDC at
boundaries, but it's important to have higher level checks to debug
holes in software sequencing to achieve quiesce conditions before
allowing an IP to be soft reset.
This is for things like ensuring there are no outstanding transactions
like a read on a bus that is still pending when the soft reset is
exercised, thereby still causing the chip to hang.
For example:
- If you have a processor, a DSP, and peripherals; and have a
problem with the DSP -- SW wants to only reset it without
resetting and reinitializing everything else in the SOC.
i.e., for partial async resets, you want to ensure your users
can achieve soft reset of an IP while the system is running
without disturbing the rest of the chip.
- The IP must first complete all transactions (or terminate them
gracefully) before going to a quiesce state to reset, so that
the SOC is fully functional after the soft reset of the IP.
No one else has this capability to go beyond formal reset checks. Real
Intent gives you a means for it. We haven't tried it yet, but it's
worth investing time to evaluate if it saves us a ton of verification
effort to validate IP soft resets in an SoC.
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I have been following Real Intent for many years.
I don't have hands-on experience with their tools, if I were in
the market for a set of formal-based tools, theirs would be worth
looking at.
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USERS ON OLDER CDC STUFF (Meridian CDC)
Meridian CDC
We assessed Real Intent Meridian CDC vs. Synopsys Atrenta Spyglass CDC.
- Spyglass CDC
Spyglass has detailed options and can deal with any situation.
However, the options are too much and very complicated.
So, some of our engineers who are not familiar with the tool
sometimes misuse it and then overlook some critical errors.
Reports a lot of false errors. As a result, our engineers pass
over the errors.
- Meridian CDC
Meridian CDC has a superior UI. Even the beginners can use
it without misuses.
Thanks to the setup error detection, the number of false errors
is dramatically decreased. It is quite helpful and useful for
entry-level engineers.
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Real Intent Meridian CDC (Clock Domain Crossing)
Meridian CDC pros
1. Quickly and easily finds CDC issues in our RTL
2. Constraint quality check: this is included in SETUP report,
like S_GENCLK, S_NOCLK and S_CONF_ENV, based on RTL and SDC
constraints. Usually, can find something useful from it.
3. CDC log file is nicely organized -- easy to locate information
on file list read in for RTL.
4. Provides list of all synchronizer cells
5. The run time and capacity are good
Meridian CDC cons
1. We've had some issues where the tool did not convert the lib
models to func/timing models correctly.
2. Reports can need filtering for noise.
3. Tool can't support multiple independent clocks passing through
MUX; additional license is required enable this feature
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Real Intent Meridian CDC
Meridian CDC takes your RTL and identifies issues relevant to clock
domain crossing.
One of its desirable features is its command-line interface for full
customizability.
This is based on discussions -- I do not have hands on experience.
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Our company is now taking a closer look at Real Intent Meridian CDC
Another engineer is doing this, I don't have direct experience. Based on
the quick demo I saw at DAC, it looked like good technology.
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Meridian CDC and Ascent Lint
We use Meridian CDC and Ascent Lint during our RTL design.
Both of them work well. Here is my feedback.
Performance
- Meridian CDC is faster than the other similar tools.
- We can get 20-30% faster than the other tools in some cases.
(It's hard to give a concrete number as the results depend
on circuit size.)
Capacity
- The capacity is enough for our designs.
I'd like to see these improvements:
- We are always looking for more speed.
- For Meridian CDC: Real Intent's iDebug/iVision has become much
faster over time than another debugger tool which we used (a
former version). Even so, we'd like to see for additional
functionality from Real Intent here.
- Real Intent's low-noise reporting seems similar to other tools
we tested. So, we hope they continue to enhance this, as fewer
"pseudo errors" is always better.
We recommend both Meridian CDC and Ascent Lint -- and use them both as a
necessary part of our RTL design process.
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USER ON OLDER LINT STUFF (Ascent Lint)
Real Intent Ascent Lint
We evaluated Real Intent Ascent Lint vs Synopsys Spyglass Lint.
- Ascent Lint is about 1.5 times faster than Spyglass.
- Ascent Lint's error detection capability is equivalent to
Spyglass.
However, thanks to Ascent Lint's excellent UI, it intercepts
misuses and thus overlooked errors.
- When migrating from Spyglass, it does take us time to translate
rules, select severity, and confirm them.
Overall, Ascent is more helpful for most of our users than Spyglass.
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We use Real Intent Ascent Lint to check our RTL code quality. My
feedback on it:
- The tool runs smoothly and setup is simple
- Its run time is good, and has never been an issue in our
projects
- It has high-reliability design rule support for industry
standard DO-254
- The GUI is good. It groups errors and warnings, and shows
useful information. The GUI is also useful for debug, showing
the location of the error in the RTL file, and it can generate
schematics to point out the cause of the error.
Real Intent's support is good and quick. We can get help when we need
it. Some of the issues of the tool are fixed very quickly, and
turnaround time is short. Some issues (e.g. interface-related) can
take longer.
Ascent Lint is good overall and generates easy-to-read results.
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Real Intent Ascent Lint
Ascent lint consumes RTL code, and then provides an analysis of coding
practices and flags bad syntax and syntax not recommended as best
practice.
Its most appealing aspect is low-noise reporting. Someone in our group
tested it and the initial results so far have confirmed it.
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P.S. TWO TOOLS MISSING: But if you're closely watching, there's 2 other
new "changing signoff bigtime" Prakash tools
- Verix SimFix, his X-pessimism tool that's supposted to
trounce Synopsys VCS Xprop in many ways. (See ESNUG 583 #2)
- Verix PhyCDC, does gate netlist level CDC (ESNUG 584 #2)
... but although we know they exist, this year's "Best of 2018" survey found
zero user comments about these 2. I know these 2 are coming, but I'm just
not seeing them on the user radar screen yet. Or are they?
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